![]() The value read from a subsystem/onboard device. The data received from an attached device. The value currently present at the DIO input lines. The value written to a subsystem/onboard device. Used to start an operation on a peripheral. Usually used to control the rate of operation of a subsystem or signal generation. The count value to be used by an internal counter. The data to be sent to an attached device. The maximum value for some internal counter. Used by peripherals that compare one value to another value. Usually used for control bits that are used often at run time, such as start or clear bits. Usually used to indicate some setting that does not change after initialization or at least changes infrequently. The value of the signal to be set at the DIO output pins. To a single peripheral while others may be used across multiple peripherals. The following tables list all possible property names. The enumeration is omitted if only one channel of that type is available on the bank.Įxample: A_7:0 indicates that the register corresponds to channels 0 to 7 on Bank A. An underscore (_) separates the channels bank designation and its enumeration. The Channel Name is a combination of the bank designation and its numeric enumeration or range enumeration. Registers may or may not be related to a specific peripheral. Note: SYS is a reserved value used for a special purpose system register. Universal asynchronous receiver-transmitter Note: When you program in C language, register names must not contain periods, colons, or spaces (like using “DIOA_190DIR” for “DIO.A_19:0.DIR”). Peripheral Type.Channel Name.Property Name Registers follow a naming scheme as described below: Universal asynchronous receiver-transmitter (UART)Įach peripheral is controlled through the use of its corresponding registers as outlined in this document.The LabVIEW ELVIS III Toolkit will also ship an FPGA personality as default, and it provides support for the following peripherals: This document contains reference information about the NI ELVIS III shipping personality which consists of predefined FPGA bitfile for you to program with NI ELVIS III. NI ELVIS III Shipping Personality Reference Button IRQ Number Register (IRQ.DI_BTN.NO).Button Falling Register (IRQ.DI_BTN.FALL).Button Rising Register (IRQ.DI_BTN.RISE).Button Enabling Register (IRQ.DI_BTN.ENA).Digital Count Register (IRQ.DIO_A_0.CNT).Digital IRQ Number Register (IRQ.DIO_x.NO).Digital Falling Register (IRQ.DIO_x.FALL).Digital Rising Register (IRQ.DIO_x.RISE).Digital Enabling Register (IRQ.DIO_x.ENA).Analog IRQ Number Register (IRQ.AI_x.NO).Analog IRQ Configuration Register (IRQ.AI_x.CNFG).Analog IRQ Hysteresis Register (IRQ.AI_x.HYSTERESIS).Analog IRQ Threshold Register (IRQ.AI_x.THRESHOLD).Receiving Multiple Bytes then Sending Multiple Bytes.Sending Multiple Bytes then Receiving Multiple Bytes. ![]() I2C Slave Address Registers (I2C.x.ADDR).I2C Configuration Registers (I2C.x.CNFG).Encoder Counter Value Registers (ENC.x.CNTR).Encoder Configuration Registers (ENC.x.CNFG).SPI Configuration Registers (SPI.x.CNFG).PWM Maximum Count Registers (PWM.x.MAX).PWM Configuration Registers (PWM.x.CNFG).Digital DMA IDLE Registers (DI.x.DMA_IDL, DO.x.DMA_IDL).Digital Output DMA Enable Registers (DO.x.DMA_ENA).Digital Input DMA Enable Registers (DI.x.DMA_ENA).Digital Divisor Registers (DI.x.DMA_CNTR, DO.x.DMA_CNTR).Analog Output Status Register (AO.SYS.STAT).Analog Value Registers (AI.x.VAL, AO.x.VAL).Analog DMA IDLE Registers (AI.x.DMA_IDL, AO.x.DMA_IDL).Analog Output DMA Enable Registers (AO.x.DMA_ENA).Analog Input DMA Enable Registers (AI.x.DMA_ENA).Analog Divisor Registers (AI.x.CNTR, AO.x.DMA_CNTR).Analog Configuration Registers (AI.x.CNFG).Function Select Registers (SYS.SELECTx).
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